The invention relates to the field of power electronics. It relates to a method for fabricating a semiconductor component with a cathode and an anode formed on a wafer, and to a semiconductor element.
In order to obtain the best possible electrical characteristics of semiconductor power switches, such as for example of an IGBT (Insulated Gate Bipolar Transistor), the thickness of the active zone of its semiconductor element must be chosen to be as small as possible.
By way of example, the thickness directly influences the on-state losses and the avalanche breakdown voltage. Therefore, semiconductor element thicknesses of 60-250 xcexcm are desirable in the case of breakdown voltages of 60-1800 V. However, such small thicknesses pose a major problem in the production of the semiconductor elements since wafers having a diameter of 100 mm or more should have a thickness of at least 300 xcexcm in order to minimize the risk of breaking during fabrication.
The prior art has usually solved this thickness problem for punch-through power semiconductors (PT) by means of the so-called epitaxy method. In this method, an electrically active layer is grown on a carrier substrate with a relatively large thickness of 400-600 xcexcm. In this case, the rule applies that the active layer must be thicker, the higher the intended dielectric strength of the semiconductor element. Applying this layers is very time-intensive and expensive, however.
For larger breakdown voltages, in the prior art, a stop layer, also called a buffer, is preferably introduced between carrier layer and electrically active zone. Said stop layer serves, in the blocking case, for abruptly decelerating the electric field before the anode and thus keeping it away from said anode, since the semiconductor element can be destroyed if the electric field reaches the anode. In combination with a transparent anode emitter, the stop layer furthermore influences the injection efficiency of the anode emitter. A thyristor with a stop layer of this type and with a transparent anode emitter is described in EP-A-0,700,095.
For the fabrication of non-punch-through power semiconductors (NPT), use is made not of the epitaxial method but rather of a method as described for example in Darryl Burns et al., NPT-IGBT-Optimizing for manufacturability, IEEE, pages 109-112, 0-7803-3106-011996; Andreas Karl, IGBT Modules Reach New Levels of Efficiency, PCIM Europe, Issue 1/1998, pages 8-12 and J. Yamashita et al., A novel effective switching loss estimation of non-punchthrough and punchthrough IGBTs, IEEE, pages 331-334, 0-7803-3993-2/1997. In this method, a relatively thick wafer without an epitaxial layer serves as starting material. Typical thicknesses are 400-600 xcexcm. In a first step, the wafer is treated on the cathode side, that is to say photolithography, ion implementation, diffusions, etchings and other processes required for the fabrication of the semiconductor element are carried out. In a second step, the wafer is reduced to its desired thickness on the side opposite to the cathode. This is done by customary techniques, generally by grinding and etching. In a third step, an anode is then indiffused on this reduced side. Although this method is more cost-effective than the epitaxy method, it leads to thicker semiconductor elements.
DE-A-198 29 614 discloses a fabrication method for a power semiconductor element based on a PT type which makes it possible to fabricate relatively thin semiconductor elements without having to employ the epitaxy method. For this purpose, a stop layer having a greater thickness than electrically necessary is introduced into a lightly doped base zone, process steps for embodying a cathodal patterned surface of the semiconductor element are then carried out and only afterward is the thickness of the stop layer reduced to the electrically required size by grinding and/or polishing. As a result, it is possible to carry out the cathodal process steps on a relatively thick wafer, thereby reducing the risk of breaking. Nevertheless, by virtue of the subsequent thinning of the wafer, a semiconductor element having the desired small thickness can be produced. The minimum thickness of the finished semiconductor elements is no longer limited by a minimum thickness that can be achieved for its starting material. What is advantageous, moreover, is that the doping of the residual stop layer is relatively low, so that the emitter efficiency can be set by way of the doping of the anode emitter.
The European patent application EP-A-1,017,093xe2x80x94still unpublishedxe2x80x94also describes such a method for fabricating a semiconductor element. This method makes it possible to fabricate relatively thin semiconductor elements having a typical thickness of 80-180 xcexcm. In this method, a doping profile which corresponds to a Gaussian profile or a complementary error function profile is preferably chosen. Consequently, after thinning, all that remains of the barrier zone is a residual zone or tail, called tail barrier zone hereinafter. The doping and then the thinning are performed in such a way that the tail barrier zone has, at its anodal surface, a doping density of at least 5xc3x971014 cmxe2x88x923, preferably 1xc3x971015 cmxe2x88x923, and, as maximum, 6xc3x971016 cmxe2x88x923, preferably 1xc3x971016 cmxe2x88x923. These values correspond to empirical values found by the applicant and are intended to avoid a negative influence on the anode efficiency.
Although good results are obtained with these empirical values, the fabrication of semiconductor elements thinned in this way is still based on the empirical values which were obtained in the fabrication of PT semiconductor elements according to the epitaxy method and in the fabrication of unthinned NPT semiconductor elements. Therefore, not all the possibilities for optimizing thinned semiconductor elements are exploited.
Therefore, it is an object of the present invention to improve the abovementioned method for fabricating a thinned power semiconductor element, so that it is possible to produce an optimized semiconductor element. In particular, it is intended that its thickness can be optimized to a respectively desired dielectric strength.
This object is achieved by embodiments of the method and semiconductor element described herein.
The invention enables a quantitative optimization of the fabrication method and thus of a thinned semiconductor clement. In said quantitative optimization, diverse parameters and their relation to one another are taken into account, in particular a dopant area density of a tail barrier zone, a dopant density at an anodal surface of the tail barrier zone, a dopant density of a base, a characteristic decay length or slope of the doping profile of the tail barrier zone, and also a thickness of a basexe2x80x94resulting from the waferxe2x80x94from anode to cathode.
In a first variant of the method, for a respectively required dielectric strength, a lower and an upper limit value are specified for the dopant area density of the tail barrier zone. In this case, the limits vary in a manner directly and/or indirectly dependent on the parameters specified above. The upper limit takes account of a characteristic decay length of the doping profile of the tail barrier zone and the lower limit takes account of a punch-through degree defined as the ratio of a punch-through voltage in accordance with formula (8) and an avalanche breakdown voltage.
In a second variant of the method, the semiconductor element is optimized by bringing the product of the doping atom density of the tail barrier zone at the surface with the characteristics decay length of the tail barrier zone into a fixed relation with the avalanche breakdown voltage,
Further advantageous variants and embodiments emerge from the dependent patent claims.